philips semiconductors product specification insulated gate bipolar transistor buk866-400 iz protected logic-level igbt general description quick reference data protected n-channel logic-level symbol parameter min. typ. max. unit insulated gate bipolar power transistor in a plastic envelope v (cl)cer collector-emitter clamp voltage 370 410 500 v suitable for surface mount v cesat collector-emitter on-state voltage 2.2 v applications. it is intended for i c collector current (dc) 20 a automotive ignition applications, and p tot total power dissipation 100 w has integral zener diodes providing e cers clamped energy dissipation 300 mj active collector voltage clamping and esd protection up to 2 kv. pinning - sot404 pin configuration symbol pin description 1 gate 2 collector 3 emitter tab collector limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v ce collecter-emitter voltage t p 500 m s - 500 v v ce collector-emitter voltage continuous -20 50 v v ge gate-emitter voltage - - 12 v i c collector current (dc) t mb = 100 ?c - 10 a i c collector current (dc) t mb = 25 ?c - 20 a i cm collector current (pulsed peak value, t mb = 25 ?c; t p 10 ms; - 25 a on-state) v ce 15 v i clm collector current (clamped inductive 1 k w r g 10 k w -10a load) e cers clamped turn-off energy t mb = 25 ?c; i c = 10 a; r g = 1 k w ; - 300 mj (non-repetitive) see figs. 23,24 e cerr clamped turn-off energy (repetitive) t mb = 125 ?c; i c = 8 a; r g = 1 k w ; - 125 mj f = 50 hz; t = 60 min. e ecr reverse avalanche energy i e = 1 a; f = 50 hz - 5 mj (repetitive) p tot total power dissipation t mb = 25 ?c - 125 w t stg storage temperature - -55 150 ?c t j operating junction temperature - -40 150 ?c esd limiting value symbol parameter conditions min. max. unit v c electrostatic discharge capacitor human body model - 2 kv voltage (100 pf, 1.5 k w ) 13 mb 2 c g e september 1998 1 rev. 1.200
philips semiconductors product specification insulated gate bipolar transistor buk866-400 iz protected logic-level igbt thermal resistances symbol parameter conditions typ. max. unit r th j-mb thermal resistance junction to - - 1.0 k/w mounting base r th j-a thermal resistance junction to minimum footprint, 50 - k/w ambient fr4 board (see fig. 26). static characteristics t mb = 25 ?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)cg collector-gate zener 2 ma -i g 5 ma; -40 t j 150?c 370 410 500 v breakdown voltage v (br)ec reverse collector-emitter i e = 10 ma 20 30 50 v breakdown voltage v (br)ges gate-emitter breakdown i g = 1 ma 12 16 20 v voltage v ge(to) gate threshold voltage v ce = v ge ; i c = 1 ma 1 1.5 2 v v ge(to) gate threshold voltage v ce = v ge ; i c = 1 ma; 0.6 - 2.4 v -40 t j 150?c i ces zero gate voltage collector v ce = 50 v; v ge = 0 v; t j = 25 ?c - 0.01 10 m a current i ces zero gate voltage collector t j = 125 ?c - 0.01 1 ma current i ec reverse collector current v ce = -20 v - 0.2 5 ma i ec reverse collector current v ce = -20 v; t j = 125?c - 2 20 ma i ges gate emitter leakage current v ge = 6 v - 0.1 1 m a t j = 150?c - 5 100 m a v cesat collector-emitter on-state v ge = 4.5 v; i c = 8 a - 1.2 2.2 v voltage v ge = 3.5 v; i c = 6 a; - 1.2 2.2 v -40 t j 150?c dynamic characteristics t mb = 25 ?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (cl)cer collector-emitter clamp voltage r g = 1 k w ; i c = 10 a; 370 410 500 v (peak value) -40 t j 150?c; inductive load; see figs. 23,24 g fe forward transconductance v ce = 15 v; i c = 4 a 5.5 15 20 s c ies input capacitance v ge = 0 v; v ce = 25 v; f = 1 mhz - 940 1200 pf c oes output capacitance - 95 130 pf c res feedback capacitance - 30 50 pf t d off turn-off delay time i c = 8 a; v cl = 300 v; r g = 1 k w ; - 13 18 m s t f fall time v ge = 5 v; t j = 125?c; - 6 10 m s t c crossover time inductive load; see figs. 20,21 - 12 - m s e off turn-off energy loss - 13 - mj september 1998 2 rev. 1.200
philips semiconductors product specification insulated gate bipolar transistor buk866-400 iz protected logic-level igbt fig.1. transient thermal impedance z th j-mb = f(t) ; parameter d = t p /t fig.2. turn-off safe operating area conditions: t j t jmax. ; r g 3 1 k w fig.3. typical on-state voltage v cesat = f(i c ); parameter t j ; conditions: v ge = 3.5 v fig.4. normalised power dissipation. pd% = 100.p d /p d 25?c = f(t mb ) fig.5. derating of i clm with turn-off dv ce /dt conditions: v ce 500 v; t j t jmax. fig.6. typical on-state voltage v cesat = f(i c ); parameter t j ; conditions: v ge = 5 v 1e-07 1e-05 1e-03 1e-01 1e+01 t / s zth(j-mb) / (k/w) 1e+01 1e+00 1e-01 1e-02 1e-03 0 0.5 0.2 0.1 0.05 0.02 d = t p t p t t p t d d= 0 20 40 60 80 100 120 140 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0 200 400 600 vce / v ic / a buk8y6-400iz 10 1 0.1 self-clamped clm i 0 50 100 150 200 dvce/dt (v/us) iclm / a buk8y6-400iz 15 10 5 0 0 4 8 12 16 20 24 ic / a vce / v pmg35a 3 2 1 0 tj / c = 150 25 -40 0 4 8 12 16 20 24 ic / a vce / v pmg35a 2 1.5 1 0.5 0 tj / c = 150 25 -40 september 1998 3 rev. 1.200
philips semiconductors product specification insulated gate bipolar transistor buk866-400 iz protected logic-level igbt fig.7. typical output characteristics i c = f(v ce ); parameter v ge ; conditions: t j = 25?c fig.8. typical transfer characteristics i c = f(v ge ), parameter t j ; conditions: v ce = 10 v fig.9. typical forward transconductance g fe = f(i c ); parameter t j; conditions: v ce = 10 v fig.10. typical gate-emitter charcteristics i ges = f(v ge ); conditions: v ce = 0 v; t j = 25?c fig.11. typical collector clamp characteristics i ces = f(v ce ); parameter t j; conditions: v ge = 0 v fig.12. gate threshold voltage v ge(to) = f(t j ); conditions: i c = 1 ma; v ce = v ge pmg35a vge / v = 4 5 4 0246810 vce / v ic / a 30 20 10 0 2 2.2 2.4 2.6 2.8 3 0 10 20 vge / v +/- iges / a pmg35a 1e-2 1e-3 ie-4 1e-5 1e-6 1e-7 1e-8 1e-9 515 0 1 2 3 4 vge / v ic / a pmg35a 30 20 10 0 tj / c = 150 25 -40 350 370 390 410 430 450 vce / v ices / ma pmg35a 10 1 0.1 tj / c = 150 25 -40 0 ic / a gfe / s pmg35a 35 30 25 20 15 10 5 0 10 20 30 tj / c = 150 25 -40 -40 -20 0 20 40 60 80 100 120 140 tj / c vge(to) / v 2.5 2 1.5 1 0.5 max. typ. min. buk856-400iz september 1998 4 rev. 1.200
philips semiconductors product specification insulated gate bipolar transistor buk866-400 iz protected logic-level igbt fig.13. sub-threshold collector current i c = f(v ge ); t j = 25?c; v ce = v ge fig.14. typical turn-on gate charge characteristics v ge = f(q g ); conditions: i c = 8 a. fig.15. typical capacitances c ies , c oes , c res c = f(v ce ); conditions: v ge = 0 v; f = 1 mhz fig.16. typical switching characteristics vs. r g conditions: t j =125 ?c; i c =8 a; v cl =300 v; l c =5 mh. fig.17. typical switching characteristics vs. t j conditions: i c =8 a; v cl =300 v; r g =1 k w ; l c =5 mh. fig.18. typical switching characteristics vs. i c conditions: t j =125 ?c v cl =300 v; r g =1 k w ; l c =5 mh. 0 0.4 0.8 1.2 1.6 2 2.4 vge / v ic / a 1e-01 1e-02 1e-03 1e-04 1e-05 1e-06 sub-threshold conduction 2 % typ 98 % 0 2 4 rg / kohm t / us, e / mj pmg35a 100 10 1 135 td(off) e(off) tf 0 10 20 30 qg / nc vge / v pmg35a 6 5 4 3 2 1 0 300 vcc / v = 12 0 100 tj / c t / us, e / mj pmg35a 15 10 5 0 50 150 td(off) e(off) tf 0.01 1 100 vce / v c / pf pmg35a 10000 1000 100 10 0.1 10 1000 cies coes cres 0 2 4 6 8 10 ic / a t / us, e / mj pmg35a 15 10 5 0 td(off) e(off) tf september 1998 5 rev. 1.200
philips semiconductors product specification insulated gate bipolar transistor buk866-400 iz protected logic-level igbt fig.19. typical turn-off dv ce /dt vs. r g conditions: t j =125 ?c; i c =8 a; v cl =300 v; l c =5 mh. fig.20. test circuit for inductive load switching times . fig.21. definitions of inductive load switching times . fig.22. reverse breakdown voltage v (br)ecs = f(t j ); conditions: i ec = 50 ma fig.23. test circuit for clamped turn-off energy test fig.24. definition of clamping energy e cer 0 2 4 rg / kohm dvce/dt (v/us) pmg35a 150 100 50 0 1 35 0 100 tj / degc v(br)ecs / v buk856-400iz 35 30 25 20 min. typ. -50 50 150 : adjust for correct ic vcc v lc d.u.t. r 0v t p 0r1 g vge ic measure cl : adjust for correct ic vcc lc d.u.t. r 0v t p 0r1 g v ic measure ge ge c ce t t td(off) tf tc 10% 90% 10% 90% v v i t t v(cl)cer i vce vge v ecer ic vce x ic p t september 1998 6 rev. 1.200
philips semiconductors product specification insulated gate bipolar transistor buk866-400 iz protected logic-level igbt mechanical data fig.25. sot404 surface mounting package. centre pin connected to mounting base. notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to smd footprint design and soldering guidelines, data handbook sc18. 3. epoxy meets ul94 v0 at 1/8". unit a references outline version european projection issue date iec jedec eiaj mm a 1 d 1 d e el p h d q c 2.54 2.60 2.20 15.4 14.8 2.9 2.1 9.65 8.65 1.6 1.2 10.3 9.7 4.5 4.1 1.40 1.27 0.85 0.60 0.64 0.46 b dimensions (mm are the original dimensions) sot404 97-06-16 0 2.5 5 mm scale plastic single-ended package (philips version of d2-pak); 2 leads sot404 e e e b d 1 h d d q l p c a 1 a september 1998 7 rev. 1.200
philips semiconductors product specification insulated gate bipolar transistor buk866-400 iz protected logic-level igbt mounting instructions dimensions in mm fig.26. sot404 : soldering pattern for surface mounting . definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1999 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 17.5 11.5 9.0 5.08 3.8 2.0 september 1998 8 rev. 1.200
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